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 EMIF03-SIM02M8
3 line IPADTM, EMI filter for SIM card applications
Features
8 1
GND

SIM card EMI low-pass filter High efficiency in EMI filtering Very low PCB space consumption: 1.7 mm x 1.5 mm Very thin package: 0.6 mm max High efficiency in ESD suppression on external pins (IEC 61000-4-2 level 4). High reliability offered by monolithic integration High reduction of parasitic elements through integration and wafer level packaging. Lead free package Easy layout and flexibility thanks to I/O topology Low clamping voltage Figure 1.
Vcc
7 6 5
2 3 4
GND
Micro QFN 1.7 mm x 1.5 mm (bottom view)
Pin configuration (top view)
Vcc
CLK in Data in
GND
RST in
RST EXT CLK EXT Data EXT
Complies with following standards
IEC 61000-4-2 level 4 external pins - 15 kV (air discharge) - 8 kV (contact discharge) IEC 61000-4-2 level 2 internal pins - 2 kV (air discharge) - 2 kV (contact discharge) MIL STD 883G - Method 3015-7 Class 3A (all pins)
Figure 2.
RST in
Device configuration
Vcc 100 R1 RST ext
CLK in
47 R2
CLK ext
Data in
100 R3
Data ext
Applications
Where EMI filtering in ESD sensitive equipment is required:

GND Maximum line capacitance = 20 pF
Keyboard for mobile phones Computers and printers Communication systems MCU boards
Description
The EMIF03-SIM02M8 is a 3 line highly integrated device designed to suppress EMI/RFI noise in all systems exposed to electromagnetic interference. This filter includes ESD protection circuitry, which prevents damage to the application when subjected to ESD surges up to 15 kV on the external pins.
TM: IPAD is a trademark of STMicroelectronics
October 2007
Rev 1
1/10
www.st.com
Characteristics
EMIF03-SIM02M8
1
Table 1.
Symbol
Characteristics
Absolute ratings (limiting values at Tamb = 25 C unless otherwise specified)
Parameter Internal pins ESD discharge IEC 61000-4-2 air discharge ESD discharge IEC 61000-4-2 contact discharge External pins and VCC ESD discharge IEC 61000-4-2 air discharge ESD discharge IEC 61000-4-2 contact discharge All pins MIL STD 883G - Method 3015-7 Class 3A (human body model) Junction temperature Operating temperature range Storage temperature range Value 2 2 15 8 4 125 -40 to + 85 -55 to +150 C C C kV Unit
VPP
Tj Top Tstg
Table 2.
Symbol VBR IRM VRM VCL IPP RI/O Cline Symbol VBR IRM R1, R3 R2 Cline
Electrical characteristics (Tamb = 25 C)
Parameter Breakdown voltage Leakage current @ VRM Stand-off voltage Clamping voltage Peak pulse current Series resistance between input and output Input capacitance per line Test conditions IR = 1 mA VRM = 3 V Tolerance 20% Tolerance 20% VR= 0 V, F = 1 MHz, VOSC = 30 mV 100 47 17 20 Min. 6 Typ.
IPP VBR VCL VRM IRM IR VF V I IF
Max. 7.9 0.2
Unit V A pF
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EMIF03-SIM02M8
Characteristics
Figure 3.
0.00
S21(db) attenuation (RST line)
Figure 4.
0.00
S21(db) attenuation (CLK line)
dB
dB
-5.00
-5.00
-10.00
-10.00
-15.00
-15.00
-20.00
-20.00
-25.00
-25.00
-30.00
-30.00
F (Hz)
-35.00 300.0k 1.0M 3.0M 10.0M 30.0M 100.0M 300.0M 1.0G 3.0G
-35.00 300.0k 1.0M 3.0M 10.0M
F (Hz)
30.0M 100.0M 300.0M 1.0G 3.0G
Figure 5.
0.00
S21(db) attenuation (DATA line)
Figure 6.
0.00 -10.00
Analog cross talk measurements
dB
dB
-5.00
-20.00 -30.00
-10.00
-40.00 -50.00
-15.00
-60.00
-20.00
-70.00 -80.00
-25.00
-90.00 -100.00
-30.00
-110.00
F (Hz)
-35.00 300.0k 1.0M 3.0M 10.0M 30.0M 100.0M 300.0M 1.0G 3.0G
F (Hz)
1.0M 3.0M 10.0M 30.0M 100.0M 300.0M DataIn-Rst/Clk 1.0G 3.0G ClkIn-RstExt
-120.00 300.0k
Figure 7.
ESD response to IEC 61000-4-2 (+15 kV air discharge) applied to external pin
Figure 8.
ESD response to IEC 61000-4-2 (-15 kV air discharge) applied to external pin
5 V/div
2 V/div
200 ns/div
2 V/div
5 V/div
200 ns/div
3/10
Application schematic
EMIF03-SIM02M8
Figure 9.
ESD response to IEC 61000-4-2 (+2 kV air discharge) applied to internal pin
Figure 10. ESD response to IEC 61000-4-2 (-2 kV air discharge) applied to internal pin
5 V/div
2 V/div
5 V/div
20 ns/div
2 V/div
20 ns/div
2
Application schematic
Figure 11. Application schematic
SIM PROCESSOR
Vcc RST in CLK in Data in Vcc RST EXT CLK EXT Data EXT
SIM CONNECTOR
3
Ordering information scheme
Figure 12. Ordering information scheme
EMIF EMI Filter Number of lines Information xxx = application zz = version Package Mx = Micro QFN x leads yy xxx zz Mx
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GND
EMIF03-SIM02M8
Package information
4
Package information
Epoxy meets UL94, V0
In order to meet environmental requirements, ST offers these devices in ECOPACK(R) packages. These packages have a lead-free second level interconnect. The category of second level interconnect is marked on the inner box label, in compliance with JEDEC Standard JESD97. The maximum ratings related to soldering conditions are also marked on the inner box label. ECOPACK is an ST trademark. ECOPACK specifications are available at: www.st.com. Table 3. QFN 1.7 x 1.5 package dimensions
Dimensions Ref Millimeters MIN A A1 b D D2 E E2 e k L 0.20 0.25 0.30 0.35 0.30 0.9 0.50 0.00 0.15 TYP 0.55 0.02 0.18 1.70 1.00 1.50 0.40 0.40 0.08 0.10 0.12 0.14 0.50 0.12 1.10 0.35 MAX 0.60 0.05 0.25 MIN 0.20 0.00 0.06 inches TYP 0.22 0.01 0.07 0.67 0.39 0.59 0.16 0.16 0.24 0.43 MAX 0.24 0.02 0.10
Figure 13. Footprint (dimensions in mm) Figure 14. Marking
HA
Dot: Pin 1 Identification
5/10
Package information Figure 15. Tape and reel specification
1.5 +/- 0.1
EMIF03-SIM02M8
2.0+/-0.05
4.00+/-0.1
1.75 +/- 0.1 3.5 +/- 0.03
0.75
8.0 +/- 0.3
XX
XX
XX
1.90
1.70 User direction of unreeling
4.00
Note:
Product marking may be rotated by 90 for assembly plant differentiation. In no case should this product marking be used to orient the component for its placement on a PCB. Only pin 1 mark is to be used for this purpose.
6/10
EMIF03-SIM02M8
Recommendation on PCB assembly
5
5.1
Recommendation on PCB assembly
Stencil opening design
1. General recommendation on stencil opening design a) Stencil opening dimensions: L (Length), W (Width), T (Thickness).
Figure 16. Stencil opening dimensions
L
T
W
b)
General Design Rule Stencil thickness (T) = 75 ~ 125 m W Aspect Ratio = ---- 1.5 T LxW Aspect Area = --------------------------- 0.66 2T ( L + W )
2.
Reference design a) b) Stencil opening thickness: 100 m Stencil opening for central exposed pad: Opening to footprint ratio is 50%. Example: Stencil opening L = 680 m, W = 300 m Footprint (see Figure 13) L = 1000 m, W = 400 m c) Stencil opening for leads: Opening to footprint ratio is 90%. Example: Stencil opening L = 570 m, W = 190 m Footprint (see Figure 13) L = 600 m, W = 200 m
5.2
Solder paste
1. 2. 3. 4. Halide-free flux qualification ROL0 according to ANSI/J-STD-004. "No clean" solder paste is recommended. Offers a high tack force to resist component movement during high speed Solder paste with fine particles: powder particle size is 20-45 m.
7/10
Recommendation on PCB assembly
EMIF03-SIM02M8
5.3
Placement
1. 2. 3. 4. Manual positioning is not recommended. It is recommended to use the lead recognition capabilities of the placement system, not the outline centering Standard tolerance of 0.05 mm is recommended. 3.5 N placement force is recommended. Too much placement force can lead to squeezed out solder paste and cause solder joints to short. Too low placement force can lead to insufficient contact between package and solder paste that could cause open solder joints or badly centered packages. To improve the package placement accuracy, a bottom side optical control should be performed with a high resolution tool. For assembly, a perfect supporting of the PCB (all the more on flexible PCB) is recommended during solder paste printing, pick and place and reflow soldering by using optimized tools.
5. 6.
5.4
PCB design preference
1. 2. To control the solder paste amount, the closed via is recommended instead of open vias. The position of tracks and open vias in the solder area should be well balanced. The symmetrical layout is recommended, in case any tilt phenomena caused by asymmetrical solder paste amount due to the solder flow away.
5.5
Reflow profile
Figure 17. ST ECOPACK(R) recommended soldering reflow profile for PCB mounting
Temperature (C)
260C max 255C 220C 180C 125 C
2C/s recommended 2C/s recommended 6C/s max 6C/s max
3C/s max 3C/s max
0 0 1 2 3 4 5
10-30 sec 90 to 150 sec 90 sec max
6
7
Time (min)
Note:
Minimize air convection currents in the reflow oven to avoid component movement.
8/10
EMIF03-SIM02M8
Ordering information
6
Ordering information
Table 4. Ordering information
Marking HA Package Micro QFN Weight 4 mg Base qty 3000 Delivery mode Tape and reel (7")
Part number EMIF03-SIM02M8
7
Revision history
Table 5.
Date 07-Oct-2007
Document revision history
Revision 1 Initial release. Changes
9/10
EMIF03-SIM02M8
Please Read Carefully:
Information in this document is provided solely in connection with ST products. STMicroelectronics NV and its subsidiaries ("ST") reserve the right to make changes, corrections, modifications or improvements, to this document, and the products and services described herein at any time, without notice. All ST products are sold pursuant to ST's terms and conditions of sale. Purchasers are solely responsible for the choice, selection and use of the ST products and services described herein, and ST assumes no liability whatsoever relating to the choice, selection or use of the ST products and services described herein. No license, express or implied, by estoppel or otherwise, to any intellectual property rights is granted under this document. If any part of this document refers to any third party products or services it shall not be deemed a license grant by ST for the use of such third party products or services, or any intellectual property contained therein or considered as a warranty covering the use in any manner whatsoever of such third party products or services or any intellectual property contained therein.
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